Input/output (I/O) and analog transistors are important for processors and system on chip (SoC) devices since these devices are connected to the outside world and require I/O transistors that support higher bias voltages. For these high voltage applications, long channel I/O transistors (having an increased channel and gate length) can be employed.
A longer gate length (as compared to nominal transistor) reduces the magnitude of the lateral electric field in the channel region beneath the gate and thus reduces hot carrier injection to prevent degradation of the transistors' electrical performance. Analog devices also use a long gate length to reduce the random-dopant-fluctuation to improve the device reliability.
Vertical field effect transistors (VFETs) are being explored as a viable device option for continued complementary metal oxide semiconductor (CMOS) scaling beyond the 7 nanometer (nm) technology node. As opposed to planar CMOS devices, VFETs are oriented with a vertical fin channel disposed on a bottom source and drain and a top source and drain disposed on the fin channel. In vertical transistors, however, it is difficult to offer different gate lengths to fabricate long channel and analog devices.
Therefore, techniques for forming different gate lengths in VTFETs would be desirable.